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This article is part of the series Embedded Digital Signal Processing Systems.

Open Access Open Badges Research Article

A SystemC-Based Design Methodology for Digital Signal Processing Systems

Christian Haubelt*, Joachim Falk, Joachim Keinert, Thomas Schlichter, Martin Streubühr, Andreas Deyhle, Andreas Hadert and Jürgen Teich

Author Affiliations

Hardware-Software-Co-Design, Department of Copmuter Sciences, Friedrich-Alexander-University of Erlangen-Nuremberg, Erlangen 91054, Germany

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EURASIP Journal on Embedded Systems 2007, 2007:047580  doi:10.1155/2007/47580

The electronic version of this article is the complete one and can be found online at: http://jes.eurasipjournals.com/content/2007/1/047580

Received:7 July 2006
Revisions received:14 December 2006
Accepted:10 January 2007
Published:20 March 2007

© 2007 Haubelt et al.

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Digital signal processing algorithms are of big importance in many embedded systems. Due to complexity reasons and due to the restrictions imposed on the implementations, new design methodologies are needed. In this paper, we present a SystemC-based solution supporting automatic design space exploration, automatic performance evaluation, as well as automatic system generation for mixed hardware/software solutions mapped onto FPGA-based platforms. Our proposed hardware/software codesign approach is based on a SystemC-based library called SysteMoC that permits the expression of different models of computation well known in the domain of digital signal processing. It combines the advantages of executability and analyzability of many important models of computation that can be expressed in SysteMoC. We will use the example of an MPEG-4 decoder throughout this paper to introduce our novel methodology. Results from a five-dimensional design space exploration and from automatically mapping parts of the MPEG-4 decoder onto a Xilinx FPGA platform will demonstrate the effectiveness of our approach.


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