SpringerOpen Newsletter

Receive periodic news and updates relating to SpringerOpen.

This article is part of the series Embedded Digital Signal Processing Systems.

Open Access Open Badges Research Article

A Shared Memory Module for Asynchronous Arrays of Processors

Michael J Meeuwsen*, Zhiyi Yu and Bevan M Baas

Author Affiliations

Department of Electrical and Computer Engineering, University of California, Davis, CA 95616-5294, USA

For all author emails, please log on.

EURASIP Journal on Embedded Systems 2007, 2007:086273  doi:10.1155/2007/86273

The electronic version of this article is the complete one and can be found online at: http://jes.eurasipjournals.com/content/2007/1/086273

Received:1 August 2006
Revisions received:20 December 2006
Accepted:1 March 2007
Published:9 May 2007

© 2007 Meeuwsen et al.

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.


  1. AW Burks, HH Goldstine, J von Neumann, Preliminary discussion of the logical design of an electronic computing instrument. in Collected Works of John von Neumann, vol. 5, ed. by Taub AH (The Macmillan, New York, NY, USA, 1963), pp. 34–79

  2. JL Hennessy, DA Patterson, Computer Architecture, A Quantitative Approach, 3rd edn. (Morgan Kaufmann, San Francisco, Calif, USA, 2003) chapter Memory Hierarchy Design OpenURL

  3. Z Yu, MJ Meeuwsen, R Apperson, et al. An asynchronous array of simple processors for DSP applications. IEEE International Solid-State Circuits Conference (ISSCC '06), February 2006, San Francisco, Calif, USA, 428–429

  4. R Banakar, S Steinke, B-S Lee, M Balakrishnan, P Marwedel, Scratchpad memory: a design alternative for cache on-chip memory inembedded systems. Proceedings of the 10th International Symposium on Hardware/Software Codesign (CODES '02), May 2002, Estes Park, Colo, USA, 73–78

  5. PR Panda, ND Dutt, A Nicolau, On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Transactions on Design Automation of Electronic Systems 5(3), 682–704 (2000). Publisher Full Text OpenURL

  6. D Patterson, T Anderson, N Cardwell, et al. A case for intelligent RAM. IEEE Micro 17(2), 34–44 (1997). Publisher Full Text OpenURL

  7. K Mai, T Paaske, N Jayasena, R Ho, WJ Dally, MA Horowitz, Smart memories: a modular reconfigurable architecture. Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA '00), June 2000, Vancouver, BC, Canada, 161–171

  8. BM Baas, A parallel programmable energy-efficient architecture for computationally-intensive DSP systems. Proceedings of the 37th Asilomar Conference on Signals, Systems and Computers (ACSSC '03), November 2003, Pacific Grove, Calif, USA 2, 2185–2192

  9. MJ Meeuwsen, O Sattari, BM Baas, A full-rate software implementation of an IEEE 802.11a compliant digital baseband transmitter. Proceedings of IEEE Workshop on Signal Processing Systems (SIPS '04), October 2004, Austin, Tex, USA, 124–129

  10. DM Chapiro, in Globally-asynchronous locally-synchronous systems, Ph, ed. by . D. thesis (Stanford University, Stanford, Calif, USA, 1994)

  11. RW Apperson, in A dual-clock FIFO for the reliable transfer of high-throughput data between unrelated clock domains, M, ed. by . S. thesis (University of California, Davis, Davis, Calif, USA, 2004)

  12. K Mai, R Ho, E Alon, et al. Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. IEEE Journal of Solid-State Circuits 40(1), 261–275 (2005). Publisher Full Text OpenURL