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This article is part of the series Design and Architectures for Signal and Image Processing 2009.

Open Access Open Badges Research Article

Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture

Jehangir Khan1, Smail Niar1*, MazenAR Saghir2, Yassin El-Hillali1 and Atika Rivenq-Menhaj1

Author Affiliations

1 Université de Valenciennes et du Hainaut-Cambrésis, ISTV2 - Le Mont Houy, 59313 Valenciennes Cedex 9, France

2 Department of Electrical and Computer Engineering, Texas A&M University at Qatar, 23874 Doha, Qatar

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EURASIP Journal on Embedded Systems 2009, 2009:175043  doi:10.1155/2009/175043

The electronic version of this article is the complete one and can be found online at: http://jes.eurasipjournals.com/content/2009/1/175043

Received:16 March 2009
Revisions received:30 July 2009
Accepted:19 November 2009
Published:15 March 2010

© 2009 The Author(s).

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents the design of an FPGA-based multiprocessor-system-on-chip (MPSoC) architecture optimized for Multiple Target Tracking (MTT) in automotive applications. An MTT system uses an automotive radar to track the speed and relative position of all the vehicles (targets) within its field of view. As the number of targets increases, the computational needs of the MTT system also increase making it difficult for a single processor to handle it alone. Our implementation distributes the computational load among multiple soft processor cores optimized for executing specific computational tasks. The paper explains how we designed and profiled the MTT application to partition it among different processors. It also explains how we applied different optimizations to customize the individual processor cores to their assigned tasks and to assess their impact on performance and FPGA resource utilization. The result is a complete MTT application running on an optimized MPSoC architecture that fits in a contemporary medium-sized FPGA and that meets the application's real-time constraints.

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