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Open Access Open Badges Research Article

Hardware-Enabled Dynamic Resource Allocation for Manycore Systems Using Bidding-Based System Feedback

Theocharis Theocharides1*, MariaK Michael1, Marios Polycarpou1 and Ajit Dingankar2

Author Affiliations

1 Department of Electrical and Computer Engineering, KIOS Research Center for Intelligent Systems and Networks, University of Cyprus, 1678 Nicosia, Cyprus

2 Client Components Group, Intel Corporation, Folsom, CA, USA

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EURASIP Journal on Embedded Systems 2010, 2010:261434  doi:10.1155/2010/261434

The electronic version of this article is the complete one and can be found online at: http://jes.eurasipjournals.com/content/2010/1/261434

Received:28 May 2010
Revisions received:6 October 2010
Accepted:13 October 2010
Published:28 October 2010

© 2010 Theocharis Theocharides et al.

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Manycore architectures are expected to dominate future general-purpose and application-specific computing systems. The ever-increasing number of on-chip processor cores and the associated interconnect complexities present significant challenges in the design, optimization and operation of these systems. In this paper we investigate the applicability of intelligent, dynamic system-level optimization techniques in addressing some manycore design challenges such as dynamic resource allocation. In particular, we introduce hardware enabled system-level bidding-based algorithms as an efficient and real-time on-chip mechanism for resource allocation in homogeneous and heterogeneous (MPSoC) manycore architectures. We have also developed a low-level simulation framework, to evaluate the proposed bidding-based algorithms in several on-chip network-connected manycore configurations. Experimental results indicate performance improvements between 8%–44%, when compared to a standard on-chip static allocation, while achieving a balanced workload distribution. The proposed hardware was synthesized to show that it imposes a very small hardware overhead to the overall system. Power consumption of the embedded mechanism as well as energy consumption due to additional network traffic for collecting system feedback are also estimated to be very small. The obtained results encourage further investigation of the applicability of such intelligent, dynamic system-level algorithms for addressing additional issues in manycore architectures.

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