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Open Access Open Badges Research Article

An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing

Christos Ttofis1*, Agathoklis Papadopoulos1, Theocharis Theocharides1, MariaK Michael1 and Demosthenes Doumenis2

Author Affiliations

1 KIOS Research Center, Department of ECE, University of Cyprus, 1678 Nicosia, Cyprus

2 SignalGeneriX Ltd, 3504 Limassol, Cyprus

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EURASIP Journal on Embedded Systems 2011, 2011:790265  doi:10.1155/2011/790265

Published: 23 January 2011


QAM is a widely used multilevel modulation technique, with a variety of applications in data radio communication systems. Most existing implementations of QAM-based systems use high levels of modulation in order to meet the high data rate constraints of emerging applications. This work presents the architecture of a highly parallel QAM modulator, using MPSoC-based design flow and design methodology, which offers multirate modulation. The proposed MPSoC architecture is modular and provides dynamic reconfiguration of the QAM utilizing on-chip interconnection networks, offering high data rates (more than 1 Gbps), even at low modulation levels (16-QAM). Furthermore, the proposed QAM implementation integrates a hardware-based resource allocation algorithm that can provide better throughput and fault tolerance, depending on the on-chip interconnection network congestion and run-time faults. Preliminary results from this work have been published in the Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010). The current version of the work includes a detailed description of the proposed system architecture, extends the results significantly using more test cases, and investigates the impact of various design parameters. Furthermore, this work investigates the use of the hardware resource allocation algorithm as a graceful degradation mechanism, providing simulation results about the performance of the QAM in the presence of faulty components.